1. Field of the Invention
The present invention generally relates to the field of metal-oxide-semiconductor (MOS) transistors, and more particularly, to a method for forming MOS transistors having strained silicon. From one aspect of the present invention, a stressed cap layer is formed on a MOS transistor after a spacer on the MOS transistor is removed. As a result, the stressed cap layer can make a structural strain, increase a drive current of the MOS transistor, and develop the performance of the MOS transistor.
2. Description of the Prior Art
As semiconductor technology advances and development of integrated circuits revolutionizes, the computing power and storage capacity for computers also increase exponentially, which further increases the expansion of related industries. As predicted by Moore Law, the number of transistors utilized in integrated circuits has been doubled every 18 months and semiconductor processes also have advanced from 0.18 micron in 1999, 0.13 micron in 2001, 90 nanometer in 2003, to 65 nanometer in 2005. As the semiconductor processes advance, how to increase the driving current for MOS transistors for fabrication processes under 65 nanometers has become a great challenge.
A variety of methods have been provided for increasing the driving current of MOS transistors. For example, US Patent Application with Publication Number 2005/0059228 teaches a method for increasing the driving current of MOS transistors. According to the US patent application, an annealing process for a nitride-oxide composite cap is performed to change a dopant distribution in the substrate, so the electron mobility in the channel is increased. As a result of this increased mobility, the device current drive is improved. Please refer to FIGS. 1-6 for the above-mentioned method. FIGS. 1-6 are schematic cross-sectional diagrams illustrating a prior art method of increasing the driving current of MOS transistor. As shown in FIG. 1, a device 300 is provided. The active regions 302 and 303 are formed in a substrate 309 by implanting an n-type dopant 310 with a specific energy and dose into the substrate 309 to achieve a suitable depth and concentration for the active regions 302 and 303. In addition, a p-type dopant implant is also performed. Such an implant places the boron dopant 315 deeper than the n-type dopant 310. Thus, a p-type channel region 301 is defined between the active regions 302 and 303. The device 300 includes a channel region 301, active regions 302 and 303, a gate oxide layer 304, a poly oxide 305, a polysilicon gate 306, and an optional thin offset spacer 311, which is typically comprised of silicon nitride.
As shown in FIG. 2, sidewall spacers 412, 413, and 414 are formed and located, adjacent to the gate oxide layer 304 and the polysilicon gate 306. Subsequently, utilizing the polysilicon gate 306, the sidewall spacers 412, 413, and 414 as a mask, an ion implantation is performed with an n-type dopant such as arsenic (As) or phosphorous (P), which forms a source region 407 and a drain region 408.
As shown in FIG. 3, the composite cap 516 is typically deposited by a low temperature chemical vapor deposition process. The composite cap 516 comprises a relatively thin liner (not shown), typically comprised of oxide or oxynitride, and a nitride layer formed on the thin liner. An example of a thickness for the thin liner is about 50 to 100 Angstroms and an example of a thickness for the nitride layer is about 300 or more Angstroms. It is noted that the composite cap 516 is selectively removed so as to not cover PMOS devices through an additional patterning step followed by combinations of wet or plasma etching.
As shown in FIG. 4, the semiconductor device 300 undergoes a rapid thermal annealing process. The purpose of the annealing process is to activate the dopants implanted for source/drain extension and source/drain, and to cure crystal damage induced by the previous active implant process. The composite cap 516 has an abundance of hydrogen in the nitride film. During the rapid thermal anneal, hydrogen is released from the nitride film and it is introduced into the surrounding structures, such as the sidewall oxide and the thin liner under the nitride. Because of the increased hydrogen concentration in the oxide from the hydrogen 617 in the nitride film, p-type dopant (e.g., boron) segregation from the channel region 301 to the spacer oxide 412 or the composite cap 516 is enhanced. As a result, there is a net boron dopant loss in the channel, which reduces the dopant pile up at the Si/SiO2 interface. Therefore, the hydrogen 617 modifies the dopant profile for the channel region and creates a retrograde profile, and improves the electron mobility for the channel region 301.
As shown in FIG. 5, the composite cap 516 is removed by etching. As shown in FIG. 6, a salicide process is performed. The formation of salicide begins after the composite cap 516 is removed. Silicide regions 818 are formed on the active regions 302 and 303, and on the polysilicon gate 306. A salicide process in which a refractory metal, such as cobalt or nickel, is deposited on the regions 818, is performed and the refractory metal reacts with the underlying polysilicon or silicon layer by an allow step forming silicide. Unreacted refractory metal is then removed.
The prior art method decreases the dopant pile to improve the electron mobility for the channel region 301, but the method is limited to the structure of the offset spacer 311, the sidewall spacer 412, the sidewall spacer 413, the sidewall spacer 414, and the composite cap 516. Thus, it can only change the dopant concentration at the interface between the channel region 301 and the polysilicon gate 306, and the development is quite restricted.
On the other hand, while the NMOS is improved, the PMOS is degraded. This is due to the dose loss at a p-type lightly-doped-drain (PLDD). Since at PLDD implant, the dopant is typically placed much closer to the surface than the “pocket” for the NMOS, the dopant loss is more substantial. The dopant loss causes an increase in the parasitic resistance in source/drain extension and source/drain region. As a result, the composite cap 516 in the prior art method cannot be applied to the PMOS, and it is still a challenge in increasing the driving current of MOS transistors.